As semiconductor devices become more highly integrated, cell capacitors for storing data in memory devices must occupy a smaller area. A cell capacitor must have sufficient capacitance so as to prevent malfunction due to a soft error or noise. Various efforts have been made to manufacture a cell capacitor in a highly integrated memory device having a capacitance of at least 30 fF or more. For example, a cylindrical cell capacitor having a maximized occupation area in the same space so as to increase its capacitance has been developed.
FIGS. 1 and 2 are sectional views illustrating a method of forming a lower electrode of a conventional cylindrical capacitor.
Referring to FIGS. 1 and 2, an interlayer insulating layer 12 is formed on a semiconductor substrate 10, and contact plugs 14 are formed at predetermined intervals in the interlayer insulating layer 12 through a conventional method. An etch barrier layer 16 and a mold oxide layer (sacrifice layer) 18 containing an electrode region S for exposing the contact plugs 14 are sequentially stacked on the contact plugs 14 and the interlayer insulating layer 12. The mold oxide layer 18 defines the height of the capacitor, and is deposited to a thickness of 1.5-2 μm, for example.
Thereafter, sidewalls of the mold oxide layer 18 exposed to the electrode region S and part of the upper surfaces of the contact plugs 14 are blanketed with a conductive layer, for example, a doped polysilicon layer for a lower electrode 20. The electrode region S is filled with a buffer oxide layer 22 so as to protect the doped polysilicon layer. The lower electrode 20 is formed in the electrode region S by planarizing the polysilicon layer and the buffer oxide layer 22 through a chemical and mechanical polishing (CMP) process or an etch-back process so that an upper surface of the mold oxide layer 18 is exposed.
The height of the capacitor, that is, the thickness of the mold oxide layer 18 may be increased so as to obtain a high capacitance. However, the increase in the thickness of the mold oxide layer 18 makes it difficult to obtain a sufficient etch selectivity between the mold oxide layer 18 and a photoresist pattern (not shown) when etching the mold oxide layer 18 to define the electrode region S. In addition, since the amount of etch gas gradually decreases toward a lower part of the mold oxide layer 18, the sidewalls of the electrode region S may have inclined profiles. That is, the circumference of the lower electrode 20 formed in the electrode region S does not increase linearly from the bottom to the top thereof. Consequently, a gap between the adjacent lower electrodes 20 may become narrow at the tops thereof, which may result in an electrical short between the lower electrodes 20.
After completion of the planarization process, the mold oxide layer 18 and the buffer oxide layer 22, which surround the lower electrode 20, are removed through wet etching. The wet etching is performed using a buffered oxide etchant (BOE) or an HF solution. After completion of the wet etching, the remaining etchant is rinsed with deionized water, and the resultant structure is dried.
Undesirably, the lower electrode 20 may become tilted or a gap between the neighboring conventional lower electrodes 20 may become bridged during the rinsing process and/or the drying process. The inclining or bridging phenomenon often occurs during the drying process.
FIG. 3 is a sectional view of a capacitor using a bridge insulating layer for preventing the bridging and tilting of the lower electrode 20, and FIG. 4 is a plan view illustrating a drawback of the capacitor shown in FIG. 3.
Referring to FIGS. 3 and 4, an upper portion of the mold oxide layer 18 shown in FIG. 1 is removed and then a bridge insulating layer 22 is formed where the removed portion was in such a way to connect the adjacent lower electrodes 20. Thereafter, the mold oxide layer 18 is removed through the rinsing process and the drying process as illustrated in FIG. 2. When the mold oxide layer 18 is removed, an electrode space V is formed below the bridge insulating layer 22 between the lower electrodes 20. The bridge insulating layer 22 prevents the lower electrodes 20 from tilting or contacting each other.
It is preferable to have a suitable etch selectivity between the mold oxide layer 18 and the bridge insulating layer 22 so as to remove the mold oxide layer 18. However, it is difficult for a conventional aqueous base etchant to provide an etch selectivity greater than 100. Accordingly, the conventional aqueous base etchant cannot provide a satisfactory etch selectivity. When the etch selectivity is small, the bridge insulating layer 22 may be thinned or removed by over-etching during the removing process for the mold oxide layer 18. When the bridge insulating layer 22 is over-etched, the tilting of or contact between the lower electrodes 20 cannot be prevented.